(1) Field of the Invention
The invention relates to semiconductor manufacturing processing, and more specifically to a method of positioning a wafer by using a new Wafer Edge Exposure (WEE) technique.
(2) Description of the Prior Art
Standard practice in positioning and aligning a wafer during wafer processing operations is to use an inspection pattern on the semiconductor wafer to determine the degree of alignment of a first device layer.
A great number of the processing steps used during the manufacturing of semiconductor devices are based on the application of photolithographic exposures. Of key importance in making successive photolithographic exposures is that successive layers of patterns are accurately aligned with respect to each other. The degree of misalignment that can occur between successive photolithographic exposures is known as pattern overlay, overlay than represents the degree of misalignment that occurs between successive layers of patterns on thin film electronic structures and the preceding layer.
The term overlay represents the relative location of features formed during different steps of the semiconductor wafer processing sequence. The overlay is a numeric quantity that is defined at every location on the substrate as the difference between a numerical value indicative of a position or location on the first formed portion of a semiconductor structure on a substrate and a numeric quantity of the corresponding point on a following or second formed portion of a semiconductor structure. Perfect alignment between the first and the second portion of the semiconductor structure requires that the overlay, as defined here, be equal to zero.
One approach in aligning wafer is to use an independent process layer, the so-called zeroth layer, as the source of reference and to align all process layers to this zeroth layer. Techniques and measuring tools are provided to measure the degree of shift that occurs in the overlay of the successive layers and patterns. All these techniques use alignment patterns of a particular design that are applied to both successive and preceding layers. The first layer used in this alignment sequence does, by its very nature, not have a reference point or pattern. This may lead to considerable problems of alignment in subsequent alignment steps.
FIG. 1 shows the Prior Art method of placing reference marks 10 on the surface of wafer 12, this top view of the wafer surface represents the previously highlighted zeroth layer process. This process places the reference marks on the surface of the substrate. Successive formations of patterns use marks 10 as alignment marks, it is a given that the overlay of the marks 10 for the successive patterns that are formed on the semiconductor substrate is zero. That is the marks 10 are, going from the preceding to the following deposition of patterns, in perfect alignment. Measured is the overlay within the successive patterns while these patterns are being created.
FIG. 2 shows the creation of a preceding pattern 14 formed on the wafer 12 by use of prior art method of chip manufacturing using two intersecting patterns 18 and 20. FIG. 2b shows a magnification of the pattern 14 as representative of the first pattern that is created on the surface of the semiconductor substrate. This pattern is created at scribe lines within the surface of the semiconductor substrate and serves as the reference pattern for the measurement of the alignment of the following patterns.
FIG. 3a shows the formation of a following or second pattern 16 on the surface of the semiconductor substrate as representative of the second pattern that is created on the surface of the semiconductor substrate. The pattern 16 is created by use of prior art method of chip manufacturing using two intersecting patterns 22 and 24. The pattern 16 (FIG. 3a) is roughly in the same geometric location on the wafer surface as the previously highlighted first pattern (pattern 14, FIG. 2a). FIG. 3b shows a magnified image where the reference pattern (pattern 14, FIG. 2a) is superimposed over the pattern that is representative of the second pattern (pattern 16, FIG. 3a). The smaller square 26 is patterned in the second pattern in the same geometric location as the reference square 28.
It is clear from FIG. 3b that in measuring values for x.sub.1, x.sub.2, y.sub.1 and y.sub.2 accurate conclusions can be drawn relating to the relative position of the second pattern (pattern 16, FIG. 3a) with respect to the first or reference pattern (patter 14, FIG. 2a). It is also clear that the alignment accuracy of following layers can be determined in the same manner.
One of the main concerns during wafer manufacturing is the control and elimination of contaminants or impurities that exist in the environment wherein the wafer is being processed. The environment can introduce these impurities or they can be created by particles that are created as part of the wafer manufacturing process itself.
Environmentally introduced impurities are typically controlled by the use of filters and extremely stringent controls of clean environment imposed within the semiconductor manufacturing area.
Contaminants introduced by the wafer that is being processed can, due to the complexity of the various processing steps combined with the variety of materials that are used during wafer processing, be of a variety of sources and a variety of materials. The method used to mechanically handle the wafer, such as wafer clamp down and wafer movement between the wafer processing stations can lead to severe stress within points of contact of the wafer. This stress can be the source of creation of contaminants.
It is clear that, in controlling wafer contaminants, the edge of the wafer is a critical area. This is the area where mechanical contact with the wafer takes place and this is therefore the area where contaminants are most likely to be created or where the further dissemination of contaminants is best controlled. One method that has been successfully used for this purpose is the chamfering or rounding off of the edges of the wafer prior to the formation of any of the active layers on the wafer. Another method that has seen application is the removing or grinding of the periphery of the wafer. Both of these methods however create, by their very nature, yet more particles that can therefore be contributing to further contamination of the wafer that is being processed.
Another method to suppress wafer contaminants is the use of building an edge around the perimeter of the wafer whereby this edge suppresses the flow of contaminants. Wafer Edge Exposure (WEE) is a process whereby the edge of a wafer is fabricated such that polishing contaminants and slurry residues are prevented from entering the scribe channels of the wafer. This is accomplished by depositing a layer of photosensitive polyimide on the surface of the wafer and mounting the wafer on a chuck. The chuck is then spun thereby exposing the outer perimeter of the wafer to a light source. Due to the negative resists characteristic of the polyimide, the exposed ring of polyimide will remain in place when the wafer is developed while the unexposed portion of the polyimide will be removed. This unexposed portion of the polyimide corresponds to the scribe line pattern on the surface of the wafer; this scribe line pattern is therefore dissolved while the ring of exposed polyimide around the periphery of the wafer remains in place. This WEE forms an edge that, together with a grinding tape, forms a seal along the perimeter of the wafer. This seal prevents contaminants and slurry remains from entering into the scribe channels.
FIG. 4 shows the Prior Art processing steps for WEE fabrication. Step 1 indicates that a layer of Photo Resist/Polyimide is deposited on the surface of the layer, the wafer is entered into a wafer stepper tool (step 2) after which the layer of PR is exposed and (step 3) the WEE is formed by holding a sharply focused source of UV light over the edge of the wafer while rotating the wafer. The entire edge of the wafer is in this manner exposed to the UV light. The layer of PR is developed (step 4) after which the created WEE is measured (step 5) to determine if any of the product dice were mistakenly exposed to the UV light. This measurement procedure uses vernier calipers to manually calibrate the WEE exposure region. The invention teaches a method whereby this manual calibration is replaced and the WEE offset value can be read directly.
U.S. Pat. No. 5,824,457 (Liu et al.) teaches a WEE process.
U.S. Pat. No. 5,723,385 (Shen) discusses WEE methods where each layer is recessed from the wafer edge.
U.S. Pat. No. 5,699,282 (Allen et al.) teaches overlay patterns.
U.S. Pat. No. 5,545,570 (Chung et al.) discloses a pattern to measure overlay shift in the first layer.